instruction cache造句
例句與造句
- If there is no instruction cache , this subroutine may be a no - op
如果在你的目標(biāo)機(jī)上，沒有指令緩存，則可能不做任何操作。 - Instruction to invalidate the instruction cache line that will contain the modified instruction
指令，使將要存放修改后指令的指令高速緩存行無效。 - On sparc and sparclite only , write this subroutine to flush the instruction cache , if any , on your target machine
只在sparc和sparclite平臺上，這一功能調(diào)用用來刷新指令緩存。 - It is a risc microprocessor , has a six - stage pipeline , with separated data cache and instruction cache
銀河ts - 1采用典型的risc結(jié)構(gòu)，六級流水線，具有獨(dú)立的指令cache和數(shù)據(jù)cache 。 - In order to gain more performance improvement 8k data cache and 8k instruction cache are used in ck510
這些改進(jìn)使c - core性能大大超過m - core 。整數(shù)運(yùn)算能力是嵌入式cpu中重要的性能指標(biāo)。 - It's difficult to find instruction cache in a sentence. 用instruction cache造句挺難的
- The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed
指令讀取器產(chǎn)生讀取位址以供快取記憶體讀取快取區(qū)塊內(nèi)的指令。 - On target machines that have instruction caches , gdb requires this function to make certain that the state of your program is stable
在有指令緩存的目標(biāo)機(jī)上， gdb需要這一函數(shù)，以確定你的程序的狀態(tài)是穩(wěn)定的。 - An instruction cache miss will occur when fetching this instruction , resulting in the fetching of the modified instruction from storage
當(dāng)取這個指令時會發(fā)生指令高速緩存失敗，結(jié)果就會從存儲器中取得修改后的指令。 - And in fact , the problem is exacerbated by the fact that a media app pushes data through the data cache much faster than a static app pushes code through the instruction cache
事實(shí)上，這是由于動態(tài)媒體程序需要以遠(yuǎn)遠(yuǎn)高于靜態(tài)程序填充指令的速度來填充數(shù)據(jù)。 - This paper presents the logic circuit design of ccu for lx - 1164 cpu chip , for ccu , data and instructions are stored in separate data and instruction caches
本人有幸在夏宏博士的指導(dǎo)下參加這一工程，承擔(dān)lx ? 1164cpu的高速緩存控制器( ccu )的邏輯設(shè)計(jì)和功能仿真。 - This paper discusses msu ' s design , implementation and verification , implements the integration of the " longtengrl " system and studies the optimization of instruction cache
本課題組設(shè)計(jì)的“龍騰r1 ”微處理器芯片，指令系統(tǒng)與motorola公司的powerpc603e兼容，體系結(jié)構(gòu)自主設(shè)計(jì)。 - The performance is improved significantly . the average ipc speedup is 6 . 9 % . 3 . prefetching policy using miss queue information is proposed by investigating instruction cache misses and data cache misses
3 .通過對指令cache和數(shù)據(jù)cache失效行為的分析,提出一種預(yù)取策略? ?結(jié)合訪存失效隊(duì)列狀態(tài)的預(yù)取策略。 - Several methods to reduce the circuit switch activity are developed . pre - visiting tag technique is used to reduce the instruction cache activity . base address locality technique is used to reduce the data cache activity
并從減少電路活動性角度出發(fā)，開發(fā)出減少指令cache功耗的預(yù)訪問技術(shù)，以及減少數(shù)據(jù)cache功耗的基地址相關(guān)技術(shù)。 - This thesis addresses itself to the designing and implementation of the multi - level memory system of dpc , including the register files , instruction cache , data cache and the on - chip memory , which is called scratch - pad sram
本文采用了多層次的存儲體系結(jié)構(gòu),包括分體寄存器文件、分離的指令、數(shù)據(jù)cache以及片上存儲器scratch - padsram 。 - It has five parts , such as integer execution unit , floating point unit ( fpu ) , instruction cache , bus interface unit and memory manage unit . the instructions are executed with pipeline way . the instruction set and i / o signals are compatible with powerpc
它由定點(diǎn)執(zhí)行單元、浮點(diǎn)單元、指令cache 、總線接口單元、存儲管理單元組成，以流水和超標(biāo)量方式執(zhí)行指令，指令集和接口時序兼容powerpc ，是典型的risc微處理器結(jié)構(gòu)。
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